One or more aspects relate in general to the field of functional testing of hardware components, and in particular to a method and a test environment for testing an integrated circuit. Still more particularly, one or more aspects relate to a data processing program and a computer program product for testing an integrated circuit.
Currently, standard automatic test pattern generation (ATPG) is used to statically test hardware components like integrated circuits as device under test (DUT). The automatic test pattern generation (ATPG) is performed by an integrated circuit tester connected to the device under test via a first interface and allows full and fast control of the test patterns and utilizes tester capabilities like parameter variations, Shmoo plots, etc. The automatic test pattern generation (ATPG) is a well-established process (DFT) using state-based standard format and/or add-speed-BIST (Build in Selftest).
Current functional testing via a second control interface of the integrated circuit requires additional hardware for providing the applicable service protocol. This includes a specially prepared device under test load board, an additional workstation, wiring, and a protocol-capable front end device.
So the functional test needs external hardware attached to the device under test via the second interface and depends on external data describing chip specifications and/or chip access methods. The device under test (DUT) is set up to a functional stability state by the integrated circuit tester via the first interface, wherein the device under test (DUT) is stimulated by an external field service processor via the second interface. The response of the device under test (DUT) is captured by the field service processor and transmitted to a companion box comprising a workstation with engineering data of the device under test, test procedures and/or scripts and an input/output terminal, for example.
With such an approach a scheduler of the used test-system, comprising the integrated circuit tester, is not in charge of providing the test pattern to the device under test. Thus the tester software and/or pattern generator no longer tracks the inner state of the device under test. Higher-level functionality of the test system like shmoo plots and parameter variations cannot be utilized. Software effort for the additional second control interface would be required to control both the front end and the device under test. The granularity of the test result is limited by the pattern quality of the external workstation, wherein the test procedures are not identical to system drivers of the integrated circuit tester. Stopping at a specific event like a failure and/or hit condition is not possible, and there is no interference with the tester scheduler. It is difficult to identify both that there is an error and the location of the error.